Germanium (Ge) is a promising candidate to enhance p-channel metal oxide silicon field transistor (MOSFET) device performance. The successful development of Ge-based field effect devices requires the integration of a high-quality dielectric with equivalent oxide thickness (EOT) less than 1 nanometer that forms an electrically well behaved semiconductor dielectric interface. Although GeOx/Ge has been found promising, the thermodynamic instability as well as the relatively low dielectric constant of GeOx requires an alternative approach. The utilization of an ultrathin Si layer, to modify the semiconductor-dielectric interface from Ge into Si, is a viable approach that has been successfully demonstrated; however, the introduction of a thin Si layer into the gate stack is incompatible with the 3D FinFET manufacturing process flow and also leads to increased EOT. It is, therefore, desirable to develop a multilayer gate-stack by atomic layer deposition (ALD), where an ultrathin GeOx layer can be thermodynamically stabilized and combined with a high-k dielectric film to meet the stringent requirement of low interface trap density and large capacitance density while maintaining a low gate leakage under the constraint of full compatibility with modern 3D FinFET geometries.
Fig. 1 In-situ spectroscopic ellipsometry data for (a) GeOx thickness showing native oxide etch with H-Plasma, (b) controlled GeOx formation with pulsed Oxygen Plasma, (c) Al2O3 cap layer deposition for diffusion barrier and nucleation layer and (d) HfO2 deposition by thermal ALD at 250°C.
An approach has been developed for obtaining high-quality HfO2/Al2O3/GeOx multilayers on Ge by plasma-enhanced atomic layer deposition (PEALD) that utilizes in-situ spectroscopic ellipsometry (SE) for real-time process monitoring and control. Native GeOx is first removed using H-plasma, followed by growth of an ultrathin GeOx layer by O-plasma anneal. An ultrathin bilayer of Al2O3 and HfO2 is subsequently deposited by thermal ALD. In-situ SE is used to monitor and control the thickness of each layer as illustrated in Fig. 1. High resolution cross-section transmission electron microscopy (HRTEM) and energy-dispersive x-ray spectroscopy (EDX) of the multilayer structure are presented in Fig. 2. Large capacitance densities with EOT below 1 nm and gate leakages below 1×10-4A/cm2 at -1V (EOT=0.7 nm) have been demonstrated in metal oxide semiconductor capacitor (MOSCAP) device structures. The multilayer 3D FinFET approach was also used in the fabrication of strained Ge quantum well FinFETs resulting in excellent device performance. Ge FinFET results with ultra-thin EOT gate stack were recently presented at the 2014 International Electron Device Meeting (IEDM) in San Francisco, CA.
Fig. 2 (a) High resolution cross-section TEM of HfO2/Al2O3/GeOx/Ge gate stack and (b) EDX line scan across the Ge gate stack.
Agrawal, A. ; Barth, M. ; Rayner, G.B. ; Arun, V.T. ; Eichfeld, C. ; Lavallee, G. ; Yu, S.-Y. ; Sang, X. ; Brookes, S. ; Zheng, Y. ; Lee, Y.-J. ; Lin, Y.-R. ; Wu, C.-H. ; Ko, C.-H. ; LeBeau, J. ; Engel-Herbert, R. ; Mohney, S.E. ; Yeo, Y.-C. ; Datta, S. “Enhancement mode strained (1.3%) germanium quantum well FinFET (WFin=20nm) with high mobility (μHole=700 cm2/Vs), low EOT (∼0.7nm) on bulk silicon substrate”, 2014 IEEE International Electron Devices Meeting (IEDM), pp. 16.4.1 - 16.4.4, 15-17 Dec. 2014 (DOI: 10.1109/IEDM.2014.7047064)